1. Field of the Invention
The present invention relates to differential signalling drivers. More particularly, this invention relates to differential signalling drivers operating at low voltages.
2. Description of the Prior Art
Differential signalling drivers are known in the art. FIG. 1 illustrates a conventional low voltage differential signalling (LVDS) driver 100. The LVDS driver is situated between a voltage supply (DVDD) 110 and ground 115. A first current source (I1) 120 connects the LVDS driver to the voltage supply DVDD 110 and a second current source (I2) 130 connects the LVDS driver to ground 115. The LVDS driver has two output nodes (also known as pads) PADP and PADN. A differential signalling line (not illustrated) has one of its paths connected to PADP and its other path connected to PADN. It is the voltage difference between PADP and PADN which defines the differential signal. PADP and PADN are connected by resistors 141 and 142. The mid-point of these two resistors defines the common mode voltage (VCM) of the LVDS driver at point 150.
The LVDS driver further comprises four switches PDP, NDN, PDN and NDP. These switches are ganged together such that PDP and NDN are switched together and PDN and NDP are switched together. Hence, in order to create a voltage differential between PADP and PADN, in a first phase switches PDP and NDN are closed whilst switches PDN and NDP are open. In this configuration, the voltage at PADP will rise and the voltage at PADN will fall. In order to invert the differential signal the pair of switches PDP and NDN are opened and the pair of switches PDN and NDP are closed. In this configuration the voltage at PADP falls and the voltage at PADN rises. Because of the switching configuration set out above, typically PDP and NDN are switched in dependence on the same switching signal, and similarly PDN and NDP are switched in dependence on the inverse of that switching signal. LVDS drivers such as that illustrated in FIG. 1 typically operate with a voltage supply of 2.5V or above.
FIG. 2 illustrates a LVDS driver system, in which a LVDS driver 200 is controlled by voltage level shifter circuitry 210 and pre-driver circuitry 220. A data signal that is desired to be transmitted by the LVDS driver is input into the voltage level shifter circuitry 210, which transforms the data signal into a suitable voltage level signal for input into pre-driver circuitry 220. Pre-driver circuitry 220 then generates the necessary switching signals for controlling the LVDS driver 200. In particular, the pre-driver circuitry 220 generates a signal on line 230 to control switch PDP (abbreviated as ‘signal PDP’ in the following), a signal on line 232 to control switch PDN (abbreviated as ‘signal PDN’ in the following), a signal on line 234 to control switch NDP (abbreviated as ‘signal NDP’ in the following) and a signal on line 236 to control switch NDN (abbreviated as ‘signal NDN’ in the following). As set out with reference to FIG. 1, the signals on lines 230 and 236 are typically one and the same signal, and the signals on lines 232 and 234 are typically the inverse of that signal. In the example illustrated in FIG. 2, switches PDP and PDN are PMOS transistors and switches NDP and NDN are NMOS transistors. External connections 240 and 245 connect to pads PADP and PADN respectively. Electrostatic discharge (ESD) circuitry is also provided, connected to pads PADP and PADN. The current source I1 is implemented by a PMOS transistor biased by predetermined voltage level BIASP and current source I2 is provided by an NMOS transistor biased by predetermined voltage level BIASN.
With the drive towards lower power consumption devices, it would be desirable to operate such a LVDS driver system at even lower supply voltage, for example at 1.8V rather than the conventional 2.5V. However, operating at 1.8V can be problematic, in particular when the LVDS driver is being switched at high frequencies. The problems occur because the common mode voltage (VCM) is allowed, according to the LVDS driver definition, to vary between 1.125V and 1.375V. When the VCM voltage drifts upwards, this results (when using a 1.8V supply) in a limited voltage across current source I1. In the worst case scenario this can be as little as 150 mV. This reduced voltage “headroom” in the current source I1 results in a lower output impedance of this current source. The voltage across current source I1 varies with the data signal and hence the current source I1 will give a greater current variation due to its lower output impedance. A greater current conducted by current source I1 in this situation has the effect that the time taken to charge one of the pads PADP or PADN is reduced with respect to the time taken to discharge the opposite pad (PADN or PADP respectively). Since the pads PADP and PADN then charge faster than they discharge, the slew rate is faster when rising than when falling. This asymmetric slew rate can be a significant problem for signal integrity as the differential nature of the differential signal is not fully respected.
This asymmetric slew is illustrated in FIG. 3, in which the time evolution of the differential signal generated by pads PADP and PADN can be seen. It can clearly be seen that there is a faster rise slew than fall slew. It will be appreciated that whilst the differential signal is reliable when the voltages at PADP and PADN are not changing, problems may arise if these signals are sampled nearer to the transition region.
Some of the problems associated with low voltage low power LVDS drivers are discussed in the article “Low Power Low Voltage LVDS Drivers” by Chen, Martinez, Nix and Robinson, IEEE JSSC Volume 40, No. 2, February 2005 and in the related U.S. Pat. No. 6,927,608.
One alternative implementation of a LVDS driver 400 discussed in the Chen et al. article is illustrated in FIG. 4. This LVDS driver differs from that illustrated in FIG. 1 by the provision of parallel current sources 420 and 430 on the voltage supply side. Voltage supply (DVDD) 410 is the same as the DVDD supply 110 in FIG. 1. A single further current source 440 connects the LVDS driver to ground 450. This LVDS driver has the advantage that it does not suffer from the asymmetric slew problem described above, yet the provision of double current sources results in double the static current consumption.
The solutions proposed by Chen et al., which involve switchable current sources, are limited in terms of the frequency of differential signal that they can transmit, due to limitations on the speed at which the current sources can be switched. Furthermore, these solutions add undesirable jitter to the system.
Feedback mechanisms to increase the output impedance of a current source are also known (such as a regulated cascode current mirror), yet these techniques do not allow fast enough switching for use in LVDS drivers such as are discussed above.
It would be desirable to provide an improved technique for low voltage differential signalling which does not suffer from an asymmetric slew rate, without resorting to parallel current sources and their consequent doubling of static current consumption.